1. Field of the Invention
Systems and methods disclosed herein relate to the field of electronic circuits and, more specifically, to systems and methods for testing digital-to-analog converter/amplifier circuits.
2. Description of the Related Art
Integrated circuits (“ICs”) are widely used as building blocks for various electronic devices and electronic apparatus. Manufacturing of ICs is typically guided by operational requirements of the various electronic devices in which the ICs will be used. For example, fabrication testing may be performed to identify operating ranges of the ICs, and the ICs are rated accordingly. Tolerance levels of ICs may also be established during fabrication testing. After determining the tolerance levels and rating the ICs in a controlled environment, the ICs may be installed in various electronic devices (referred to hereafter as “field implementation”) where the ICs are expected to operate at their rated clock speeds during their entire lifetime.
To ensure that electronic devices in a field are operating at optimum levels while maintaining minimum necessary power consumption, there is a need to monitor the operation of components within the electronic devices. With reference to FIG. 1, one such component is a conventional digital-to-analog converter/amplifier circuit 100 (referred to hereafter as “DAC/amplifier circuit”). As illustrated in FIG. 1, DAC/amplifier circuit 100 may include a DAC 102 and an amplifier 104. A digital input may be provided at a terminal 106 of DAC 102. DAC 102 is configured to convert the digital input into an analog output that is provided to a terminal 108 of amplifier 104. Amplifier 104 may then amplify the analog signal and may output the amplified signal at terminal 110.
DAC/amplifier circuit 100 may be used in a variety of conventional devices, including electron-beam (e-beam) mask writing devices. Such e-beam mask writing devices are used to fabricate masks for use in semiconductor device fabrication. DAC/amplifier circuits such as circuit 100 are typically used in an e-beam mask writing device to generate analog voltages applied to beam deflection plates. To ensure that such masks are being generated accurately by the e-beam writing device, DAC/amplifier circuit 100 may be calibrated to operate with a fixed settling time and with minimal offset errors. As used herein, settling time is the interval between application of or change in a digital value to a DAC and the time at which the analog output is reached within a predetermined range. Also as used herein, offset error of a DAC is its analog output in respect to a digital input of all zeros. Thus, with regard to calibration, for example, following an application of or change in digital input at terminal 104, the settling time of DAC/amplifier circuit 100 is a time required for the amplified analog output to be reached at an amplifier output 110 within an error tolerance range of an ideal final value. When the settling time is not equal to a calibrated value, DAC/amplifier circuit 100 may be said to have a settling error.
In addition, if the amplified output at output terminal 110 is outside an error tolerance range, the DAC/amplifier circuit 100 may be said to have an offset error. An e-beam mask writer may have multiple DAC/amplifier circuits and the accuracy with which masks are generated may be greatly affected if one or more of the DAC/amplifier circuits malfunction. For example, if one or more DAC/amplifier circuits within an e-beam mask writer malfunction and the malfunctioning is not detected, the malfunctioning could result in generation of masks containing errors. Such error-containing masks would be unsuitable for use in fabrication of semiconductor devices. Detecting mask errors typically requires the use of expensive mask inspection tools and increases the overall cost of fabricating ICs.
One conventional method of monitoring the performance of DAC/amplifier circuits of an e-beam mask writer is offline testing. In accordance with such offline testing, the e-beam writer is taken offline and the DAC/amplifier circuits therein are monitored and tested by applying fixed parameters, such as fixed input voltages. Thus, offline testing delays the fabrication of masks, further contributing to the cost of manufacturing semiconductor devices.
Embodiments consistent with the present invention are directed to overcoming one or more of the above noted disadvantages of the prior art.